Modern wireless communications systems including spectrum efficient modulation schemas such as Wideband Code Division Multiple Access (WCDMA), Orthogonal Frequency Division Multiplexing (OFDM) have high peak to average ratio signals. The typical peak to average ratio of the signals in 3G and 4G Long Term Evolution (LTE) systems ranges from 6 dB to 12 dB.
The RF power amplifiers used in wireless communication systems are required to have higher efficiency and linearity to handle such a high peak to average ratio signal. As generally there is a trade-off between the efficiency and linearity. RF power amplifiers achieve the highest efficiency and the worst linearity at the saturation level. At low power level which is also called back-off level, the linearity becomes better while the efficiency decreases. In order to increase the efficiency at back-off level, the load of the amplifier can be changed dynamically according to the level of the input signal, which defined as load modulation. Some well-known examples of load modulation techniques are those used in the Doherty amplifiers and the Chireix-outphasing amplifiers.
The Doherty amplifier, which was first proposed by W. H. Doherty in 1936, is widely used in modern wireless communication systems as it provides higher efficiency over an extended output power range. FIG. 1 illustrates the structure of the conventional Doherty amplifier comprising carrier and peaking amplifier branches combined into a common load. The carrier amplifier is also defined as the main amplifier and biased at Class AB or B, and the peaking amplifier is also defined as the auxiliary amplifier and biased at Class C. The load at the combining node is Z0/2 where Z0 is the matched impedance of the carrier and peaking amplifiers for maximum power and efficiency.
The applied input signal is split by an input power divider. The carrier amplifier is fed directly from the input power divider; whereas the peaking amplifier is connected via the input offset line. The input offset line length is adjusted for phase compensation with the carrier amplifier. The outputs of the carrier and peaking amplifiers are combined into the load via the output offset lines and an impedance inverting network. At the low power levels below a threshold point, only the carrier amplifier is in operation and the peaking amplifier is non-conductive and presents high impedance in ideal conditions. But in practice, with the effect of the package parasitics and matching elements the non-conductive output impedance of the peaking amplifier shifts. Therefore an output offset line is line required in order to have high impedance at the combining node when the peaking amplifier is non-conductive. The output offset line of the carrier amplifier has the same length as the peaking output offset line for phase coherence. The impedance inverting network is configured using a quarter-wavelength line with a characteristic impedance of Z0. For low power levels below the threshold point, the impedance inverting network converts the load impedance Z0/2 to 2Z0. When presented with 2Z0 load impedance, the carrier amplifier reaches saturation at a power level lower than the rated peak power. This threshold level where the first peak efficiency point is achieved is defined as 6 dB back-off level for a 2-way symmetrical Doherty amplifier.
As the power level increases above the threshold point, the peaking amplifier starts to conduct and the supplied current from the peaking amplifier modulates the load seen by the main amplifier. The current driven by the peaking amplifier increases the voltage on the load, and the impedance seen by the main amplifier gets decreased via the impedance inverting network. As the input signal is increased further both amplifiers will be presented with Z0 and maximum combined power with maximum efficiency is obtained.
Doherty amplifiers are expected to exhibit higher efficiency over an extended output power range without any degradation in gain and linearity characteristics with respect to the same periphery class AB amplifier. In practice, conventional Doherty amplifiers utilizing Si LDMOS or GaN devices achieve lower gain and linearity than the same periphery class AB amplifiers. Biasing the peaking amplifier at class C decreases the total gain of the conventional Doherty amplifier. For the same input voltage level, the output current level of a class C biased amplifier is lower than the same amplifier biased as class B or AB. As the carrier amplifier is allowed to reach saturation at the threshold point which is at least 6 dB below the maximum output power level, the non-linearity produced by the conventional Doherty amplifier is higher than the class AB amplifier with the same periphery. Furthermore, the peaking amplifier operating at class C causes additional non-linearity to the conventional Doherty amplifier characteristics. Nevertheless, for an ideal Doherty amplifier, the carrier amplifier gain compression characteristics and the peaking amplifier gain expansion characteristics can be regarded as correspondingly matched to produce a combined linear behavior. However, considering the trans-conductance (gm) characteristics of the transistors based on the bias and input voltage level and the output-conductance characteristics of the transistors based on the load-line, it is not easy to obtain a matched gain compression and expansion curves for the carrier and peaking amplifiers.
Without concerning the linearity issue and focusing on the efficiency enhancement of the Doherty amplifier, the peaking amplifier is desired to conduct above the threshold point where the carrier amplifier reaches saturation. So, the input power division ratio, the bias points of the carrier and peaking amplifiers must be strictly configured to achieve higher efficiency over an extended output power range.
A common technique to improve the efficiency, gain and linearity properties of the Doherty amplifiers is known as “Bias-adapted Doherty amplifier”. FIG. 2 illustrates the block diagram of the bias-adapted Doherty amplifier. This technique utilizes analog or digital circuits to control the input power and/or the bias level of the peaking amplifier according to the input signal level. Control circuits first detect the envelope of the input signal level and change the input power and/or the bias point of the peaking amplifier above a predetermined threshold point. Bias adaptation schemes require extra analog, digital circuit periphery and especially for wide instantaneous bandwidth applications, the delay and the speed of the control circuits become more critical in terms of extra additional power dissipation. The main drawback of this technique is the challenge of shaping the peaking amplifier behavior without using any feedback from the carrier amplifier.
The conventional feed-forward linearization technique utilizes the output characteristics of the main amplifier and provides a high level of linearization while disregarding any concern for efficiency. FIG. 3 illustrates the schematic diagram of the feed-forward amplifier. There are 2 loops; first is the cancellation loop and second is the correction loop. In the cancellation loop, the forward output signal of the main amplifier is sampled by a coupler and subtracted from the input signal to obtain only the non-linear products of the main amplifier. In the correction loop, these non-linear products are amplified by an error amplifier and combined with the main amplifier output by an output coupler. Although this technique provides a good linearization, because of the DC power wasted by the error amplifier and the lack of any efficiency enhancement schema such as load modulation, feed-forward amplifiers provide a low level of efficiency and are not widely preferred in modern wireless communication systems.